Hybrid multi-architecture debugging with GDB

As the single-thread performance of general purpose processors no longer increases as quickly as it did in the past, system designers more and more look into alternative solutions to provide additional processing power to solve application problems. One trend that has been emerging, and proves to continue with future processors and systems that are currently under development, is to augment general processors with "accelerators" to take on special-purpose tasks. Depending on the system, these accelerators can be provided on the main processor chip itself, as an I/O-attached device, or as a separate system accessed via the network.

In some such hybrid systems, the accelerator elements are directly programmable by the user, resulting in applications that actually use more than one instruction set architecture at a time. Examples include the Cell Broadband Engine architecture with its Synergistic Processor Elements, and the use of graphics processors for general-purpose computing e.g. via the new OpenCL standard. To keep the complexity of software development for hybrid systems managable, one important question is how such hybrid applications can be efficiently debugged. This paper examines how GDB can be employed to help address this challenge.

We will focus on the question how to adapt GDB to be able to debug applications running on more than one instruction set architecture. This requires fundamental changes to GDB internals that have been worked on for many years, and are close to completion at this point. Based on this effort, we will show how special solutions that were developed to address debugging the Cell Broadband Engine and hybrid systems based on it, like the Los Alamos "Roadrunner" supercomputer, can now be integrated back into mainline GDB. We will also explore how these capabilites can be extended to cover a broader range of hybrid multi-architecture debugging challenges in the future.

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